This invention relates generally to the smoothing of thin films, and, more particularly to the smoothing and uniformity enhancement of thin films on insulators by a gas cluster ion beam (GCIB) apparatus.
Growth in integration and power consumption levels of integrated circuits (ICs) and the increase in space and portable electronics applications have stimulated significant efforts in the area of radiation hardened, low power electronics (LPE). Special technology and circuit architecture is under investigation for implementation of radiation hard LPE which operate at low supply voltages and consume low power levels without sacrificing performance. Silicon-On-Insulator (SOI) substrates have advantages which make it attractive for applications that require tolerance to radiation effects. In addition, use of SOI is a primary approach to simultaneously achieve the increased circuit density, reduced power consumption, and improved performance of SRAM""s in a cost effective and timely manner. Recent advances in SOI applications include radiation-hardened memories for space applications, Bi-CMOS, low power electronics, analog and digital circuitry, smart power devices, as well as high-temperature ( greater than 350xc2x0 C.) and cryogenic applications. Such applications for SOI material have made use of the substrates widespread.
There are many SOI substrate (wafer) types available on the market today. For example, the SOI wafer may be fabricated by several methodsxe2x80x94separation-by-implanted-oxygen (SIMOX) SOI, various forms of bond-and-etch-back SOI (BE-SOI), hydrogen-implant-and-release silicon (also known as SMART CUT(copyright) SOI, xe2x80x9cSMART CUTxe2x80x9d is a registered trademark of S.O.I. TEC Silicon On Insulator Technologies S.A.), or by plasma implanting oxygen into silicon, etc. SIMOX and BE-SOI are the most widely used SOI materials, but Smart Cut(copyright) SOI is becoming more widespread. Great simplification and consequent reduction in semiconductor fabrication costs would be achieved during fabrication of many products if the starting SOI substrate wafers were consistent from wafer to wafer and/or batch to batch.
A significant problem encountered in the commercial application of SOI substrates is the inconsistency of the gate oxide integrity (GOI) and the buried oxide integrity of CMOS circuitry. For large-scale integration, consistency in gate oxide characteristics and intrinsic break down voltages of the buried oxide are required for device and circuit operating consistency. The general threshold-voltage uniformity of SOI devices would be greatly assisted if the starting ultra-thin silicon layer could be uniform to less than 25 angstroms (xc3x85) across an SOI wafer. The inconsistency of the gate-oxide integrity has been attributed in large part to the starting SOI-wafer surface roughness. General threshold-voltage uniformity of transistor devices fabricated from SOI wafers is dependent upon the thickness uniformity of the overlying (top) silicon layer (thin film).
Thus, a major issue that must be addressed is the surface quality of the top, ultra-thin silicon layer on SOI substrates or other types of thin film substrates. Surface roughness (spatially varying topography) is typically measured by analysis of measurements formed with an atomic force microscope (AFM), imaging optical interferometer, or a transmission-electron microscope (TEM). The thickness uniformity of the silicon film can be observed by the unaided eye as color fringes for any non-uniformity greater than about 25 xc3x85. For greater precision, an imaging optical interferometer, a mapping spectroscopic ellipsometer can be employed. While bulk silicon wafers, such as utilized in standard IC manufacturing, have surface roughness of typically less than 1 xc3x85, SOI wafers are known to have a minimum surface roughness of about 3 xc3x85 to 50 xc3x85, across the wafer in the final state of SOI fabrication. This non-uniformity is consistent within a lot or xe2x80x9cbatchxe2x80x9d of wafers with the same lot number, i.e., the same manufacturing run. In the case of SIMOX, the surface roughness and non-uniformity is caused by the oxygen-ion implantation process, whereby a mono-energetic beam of oxygen atoms and molecules is implanted xcx9c200 nm below the original surface of a silicon wafer, as well as the required subsequent thermal anneal to heal defects deep in the thin film. In the case of BE-SOI, the surface roughness and non-uniformity are caused by an etch-back process that inherently leaves substantial non-uniformity of the silicon layer unless extraordinary steps are taken. In the case of the SMART CUT(copyright) SOI, a cleavage process (following the hydrogen implant) leaves many atomic steps on the silicon surface. Early indications of the plasma implantation process of SOI substrate fabrication reveal sub-surface damage and non-uniformity of the silicon and insulating layers due to the random ionization charges of the penetrating oxygen ions.
Silicon-on-insulator material poses unique problems for smoothing of the silicon surface. The method applied to smooth or provide uniform silicon layers must not contribute significant quantities of metal contamination, (typically required to be less than 9xc3x971010 atoms/cm2 total metal content), and must remove a minimal of surface silicon so as to avoid removing the thin silicon layer. Traditional bulk smoothing methods, while satisfactory for silicon films on the order of microns thick, cannot be applied to SOI films having silicon as thin as 10 to 20 nm, such as will likely be required for advanced devices.
Historically, plasma polishing has been used to reduce roughness of silicon in the semiconductor field, but owing to non-uniformity and sub-surface damage associated with plasma polishing, touch polishing has largely replaced plasma polishing in the more critical applications.
A recent study (W. Maszara, et al., Quality of SOI film after surface smoothing with H annealing, touch polishing, Proc. 1997 IEEE Int""l. SOI Conf., Oct. 6-9, 1997, p. 130) of gate oxide integrity on SOI wafers implemented hydrogen annealing and touch polishing in order to examine the effect of surface roughness on gate oxide integrity. For example, an 1150xc2x0 C./1 hour hydrogen anneal removed xcx9c10 nm to 15 nm of Si from the surface, and their touch polish method removed xcx9c50 nm to 75 nm of silicon. For a 50 nm to 200 nm thick silicon layer of SIMOX, such a large amount of silicon removal is significant and, in most commercial use cases, unacceptable. Maszara concluded that the SOI surface thickness variation is presently on the order of 0.3 nm to 1.5 nm. This constitutes as much as 15% thickness variation of a 10 nm gate oxide, and the resulting gate threshold voltage variations are likely to be unsuitable for advanced circuitry. Furthermore, the surface roughness of the SOI structure may provide dangling silicon bonds that contribute to surface charges trapped in the gate oxide/silicon interface. These may, in turn, affect the radiation hardness or general threshold voltage behavior of the circuitry.
The concept of using GCIB""s for dry etching, cleaning, and smoothing of hard materials is known in the art and has been described by Deguchi, et al. in U.S. Pat. No. 5,814,194, xe2x80x9cSubstrate Surface Treatment Methodxe2x80x9d, 1998. Because ionized clusters containing on the order of thousands of gas atoms or molecules may be formed and accelerated to modest energies on the order of a few thousands of electron volts, individual atoms or molecules in the clusters each only have an average energy on the order of a few electron volts. It is known from the teachings of Yamada, U.S. Pat. No. 5,459,326, that such individual atoms are not energetic enough to significantly penetrate a surface to cause the residual sub-surface damage typically associated with plasma polishing. Nevertheless, the clusters themselves are sufficiently energetic (some thousands of electron volts) to effectively etch, smooth, or clean hard surfaces.
Because the energies of individual atoms within a gas cluster ion are very small, typically a few eV or less, the atoms penetrate through only a few monolayers, at most, of a target surface during impact. All of the energy carried by the entire cluster ion is consequently deposited into an extremely small volume at the impact site during a period as short as about 10-12 second. Because of the high total energy of the cluster ion and extremely small interaction volume, the deposited energy density at the impact site is far greater than in the case of bombardment by conventional ions and resulting thermal spike conditions are greatly enhanced. Computer simulations have suggested instantaneous temperatures of the order of 105 oK together with megabar instantaneous pressures at cluster ion impact sites. The extreme instantaneous temperature and pressure conditions, in combination with intimate mixing between gas atoms from the cluster ion and the target material atoms, is considered to be responsible for highly enhanced chemical reaction effects. Enhanced chemical reaction effects previously reported have included oxidation effects produced by O2 and CO2 cluster ions. SiO2 dielectric layers of controllable thickness have been successfully produced on silicon at room temperature. High quality, ultra-smooth PbO films have been deposited on glass, and high conductivity indium-tin-oxide transparent conductor films have been deposited at room temperature.
It is therefore an object of this invention to provide methods and apparatus for smoothing the surface of a workpiece such as a SOI wafer.
It is therefore an object of this invention to provide methods and apparatus and for making the silicon film of an SOI wafer more uniform in thickness.
It is a further object of this invention to provide methods and apparatus for making the surface of a workpiece such as, for example, the silicon film of an SOI wafer cleaner and more free from contaminants.
The objects set forth above as well as further and other objects and advantages of the present invention are achieved by the embodiments of the invention described hereinbelow.
The present invention provides apparatus and methods to carry out the task of both reducing the surface roughness (smoothing) and improving the thickness uniformity of a workpiece, preferably, but not limited thereto, the top silicon film of a silicon-on-insulator (SOI) wafer or similar thin-film electronic and photonic materials. The invention also provides methods and apparatus for smoothing the surface of a workpiece, preferably, but not limited to a SOI wafer and for making the surface of the workpiece such as a silicon film of, preferably, a SOI wafer cleaner and more free from contaminants. The SOI may be any of the following types: the separation-by-implanted-oxygen (SIMOX), bond-and-etch-back (BE-SOI), or hydrogen-implant-and-release silicon (also known as SMART CUT(copyright) SOI), as well as other types of SOI material, all of which pose unique challenges due to the required thinness and uniformity of the silicon layer, together with its high crystalline quality, very high purity, and lack of surface roughness.
The invention utilizes a vacuum GCIB etching and smoothing process and includes a GCIB apparatus that irradiates the SOI wafer surface. Measurements performed upon the workpiece provide information on the roughness and thickness non-uniformity and on processing induced changes in roughness and thickness non-uniformity. The information is fed back to control processing by the GCIB apparatus to improve the surface until desired surface characteristics have been obtained.
For a better understanding of the present invention, together with other and further objects thereof, reference is made to the accompanying drawings and detailed description and its scope will be pointed out in the appended claims.